1. Field of the Invention
The present invention relates to technology for non-volatile storage.
2. Description of the Related Art
Non-volatile semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate and channel regions are positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors connected in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a circuit diagram of one example of a NAND string. The NAND string depicted in FIG. 1 includes four transistors (or memory cells) 100, 102, 104 and 106 in series and sandwiched between a first (or drain) select gate 120 and a second (or source) select gate 122. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line contact 128. Select gate 120 is controlled by applying the appropriate voltages to select line SGD. Select gate 122 is controlled by applying the appropriate voltages to select line SGS. The four transistors 100, 102, 104 and 106 are positioned in a common p-well. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate that form a floating gate stack. The control gates are connected to word lines (e.g., WLO-WL3). In some embodiments, the word lines are the control gates.
Although FIG. 1 shows four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string. Additionally, in some embodiments, types of charge storage layers other than floating gates can also be used. One example of a charge storage layer other than a floating gate is a charge trapping layer made from silicon nitride (“nitride”), or other suitable material.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique for Non-Volatile Memory;” U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory;” and U.S. Pat. No. 6,888,758, titled “Programming Non-Volatile Memory,” all three cited patents are incorporated herein by reference in their entirety.
In many cases, the program voltage is applied to the control gate as a series of pulses (referred to as programming pulses), with the magnitude of the pulses increasing at each pulse. Between programming pulses, a set of one or more verify operations are performed to determine whether the memory cell(s) being programmed have reached their target level. If a memory cell has reached its target level, programming stops for that memory cell. If a memory cell has not reached its target level, programming will continue for that memory cell.
At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. FIG. 2 illustrates example threshold voltage distributions for the memory cell array when each memory cell stores two bits of data. Other embodiments, however, may use more or less than two bits of data per memory cell. A system that stores three bits of data in a memory cell would utilize eight threshold voltage distributions. FIG. 2 shows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B and C for programmed memory cells are also depicted.
Each distinct threshold voltage range of FIG. 2 corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, “Tracking Cells For A Memory System,” describe various data encoding schemes for multi-state flash memory cells.
FIG. 2 shows three read reference voltages, Vra, Vrb and Vrc, for reading data from memory cells. By testing whether the threshold voltage of a given memory cell is above or below Vra, Vrb and Vrc, the system can determine what state the memory cell is in.
FIG. 2 also shows three verify reference voltages, Vva, Vvb and Vvc. When programming memory cells to state A, the system will test whether those memory cells have a threshold voltage greater than or equal to Vva. When programming memory cells to state B, the system will test whether the memory cells have threshold voltages greater than or equal to Vvb. When programming memory cells to state C, the system will determine whether memory cells have their threshold voltage greater than or equal to Vvc.
In some embodiments, threshold voltage distribution E of FIG. 2 includes memory cells with negative threshold voltages and threshold voltage distributions A-C includes memory cells with positive threshold voltages. In other embodiments more than one threshold voltage distribution will include negative voltages. In those instances, it may become necessary to test for negative threshold voltage values. In some implementations, testing for negative threshold voltages requires a different voltage be applied to p-well for a NAND string than is applied when testing for a positive voltage or when programming.
The changing of the voltage applied to be p-well can, however, negatively impact performance because the p-well has a large area and, thus, a larger resistance. This larger resistance causes the new p-well voltage to be unstable for a period of time. As a result, the storage system must wait for the p-well voltage to stabilize before proceeding. This waiting reduces the performance of the storage system.